/*
 *
 * Filename: ./regsocotp.h
 *
 * Description: PIO Registers for OCOTP interface
 *
 * Xml Revision: 1.12
 *
 * Template revision: 1.3
 *
 *
 *
 * Copyright (C) Freescale Semiconductor Unpublished
 *
 * Freescale Semiconductor
 * Proprietary & Confidential
 *
 * This source code and the algorithms implemented therein constitute
 * confidential information and may compromise trade secrets of SigmaTel, Inc.
 * or its associates, and any unauthorized use thereof is prohibited.
 *
 *
 *
 * WARNING!  THIS FILE IS AUTOMATICALLY GENERATED FROM XML.
 *                DO NOT MODIFY THIS FILE DIRECTLY.
 *
 *
 *
 * The following naming conventions are followed in this file.
 *      XX_<module>_<regname>_<field>
 *
 * XX specifies the define / macro class
 *      HW pertains to a register
 *      BM indicates a Bit Mask
 *      BF indicates a Bit Field macro
 *
 * <module> is the hardware module name which can be any of the following...
 *      USB20 (Note when there is more than one copy of a given module, the
 *      module name includes a number starting from 0 for the first instance
 *      of that module)
 *
 * <regname> is the specific register within that module
 *
 * <field> is the specific bitfield within that <module>_<register>
 *
 * We also define the following...
 *      hw_<module>_<regname>_t is typedef of anonymous union
 *
 */

#ifndef _OCOTP_H
#define _OCOTP_H  1
#include "OCOTP.h"
//#include "regs.h"

//
// common register types
//

#ifndef __LANGUAGE_ASM__
typedef unsigned char  reg8_t;
typedef unsigned short reg16_t;
typedef unsigned int   reg32_t;
#endif


//#ifndef REGS_OCOTP_BASE
//#define REGS_OCOTP_BASE (REGS_BASE + 0x021bc000)
//#endif

/*
 * HW_OCOTP_CTRL - OTP Controller Control Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned ADDR            :  7;
        unsigned RSVD0           :  1;
        unsigned BUSY            :  1;
        unsigned ERROR           :  1;
        unsigned RELOAD_SHADOWS  :  1;
        unsigned CRC_TEST        :  1;
        unsigned CRC_FAIL        :  1;
        unsigned RSVD1           :  3;
        unsigned WR_UNLOCK       : 16;
    } B;
} hw_ocotp_ctrl_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_CTRL register
 */
//#define HW_OCOTP_CTRL_ADDR      (0x021bc000)
//#define HW_OCOTP_CTRL_SET_ADDR  (0x021bc004)
//#define HW_OCOTP_CTRL_CLR_ADDR  (0x021bc008)
//#define HW_OCOTP_CTRL_TOG_ADDR  (0x021bc00c)

#define HW_OCOTP_CTRL_ADDR      (OCOTP_CTRL)
#define HW_OCOTP_CTRL_SET_ADDR  (OCOTP_CTRL_SET)
#define HW_OCOTP_CTRL_CLR_ADDR  (OCOTP_CTRL_CLR)
#define HW_OCOTP_CTRL_TOG_ADDR  (OCOTP_CTRL_TOG)


#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_CTRL           (*(volatile hw_ocotp_ctrl_t *) HW_OCOTP_CTRL_ADDR)
      #define HW_OCOTP_CTRL_RD()      (HW_OCOTP_CTRL.U)
      #define HW_OCOTP_CTRL_WR(v)     (HW_OCOTP_CTRL.U = (v))
      #define HW_OCOTP_CTRL_SET(v)    ((*(volatile reg32_t *) HW_OCOTP_CTRL_SET_ADDR) = (v))
      #define HW_OCOTP_CTRL_CLR(v)    ((*(volatile reg32_t *) HW_OCOTP_CTRL_CLR_ADDR) = (v))
      #define HW_OCOTP_CTRL_TOG(v)    ((*(volatile reg32_t *) HW_OCOTP_CTRL_TOG_ADDR) = (v))
   #else 
      #define HW_OCOTP_CTRL_RD()      (_rbase->mem32_read(HW_OCOTP_CTRL_ADDR))
      #define HW_OCOTP_CTRL_WR(v)     (_rbase->mem32_write(HW_OCOTP_CTRL_ADDR,(v)))
      #define HW_OCOTP_CTRL_SET(v)    (_rbase->mem32_write(HW_OCOTP_CTRL_SET_ADDR,(v)))
      #define HW_OCOTP_CTRL_CLR(v)    (_rbase->mem32_write(HW_OCOTP_CTRL_CLR_ADDR,(v)))
      #define HW_OCOTP_CTRL_TOG(v)    (_rbase->mem32_write(HW_OCOTP_CTRL_TOG_ADDR,(v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_CTRL bitfields
 */
/* --- Register HW_OCOTP_CTRL, field WR_UNLOCK */

#define BP_OCOTP_CTRL_WR_UNLOCK      16
#define BM_OCOTP_CTRL_WR_UNLOCK      0xFFFF0000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_CTRL_WR_UNLOCK(v)   ((((reg32_t) v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK)
#else
#define BF_OCOTP_CTRL_WR_UNLOCK(v)   (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_WR_UNLOCK(v)   (HW_OCOTP_CTRL.B.WR_UNLOCK = (v))
#endif

#define BV_OCOTP_CTRL_WR_UNLOCK__KEY  0x3E77

/* --- Register HW_OCOTP_CTRL, field RSVD1 */

#define BP_OCOTP_CTRL_RSVD1      13
#define BM_OCOTP_CTRL_RSVD1      0x0000E000

#define BF_OCOTP_CTRL_RSVD1(v)   (((v) << 13) & BM_OCOTP_CTRL_RSVD1)
/* --- Register HW_OCOTP_CTRL, field CRC_FAIL */

#define BP_OCOTP_CTRL_CRC_FAIL      12
#define BM_OCOTP_CTRL_CRC_FAIL      0x00001000

#define BF_OCOTP_CTRL_CRC_FAIL(v)   (((v) << 12) & BM_OCOTP_CTRL_CRC_FAIL)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_CRC_FAIL(v)   BF_CS1(OCOTP_CTRL, CRC_FAIL, v)
#endif

/* --- Register HW_OCOTP_CTRL, field CRC_TEST */

#define BP_OCOTP_CTRL_CRC_TEST      11
#define BM_OCOTP_CTRL_CRC_TEST      0x00000800

#define BF_OCOTP_CTRL_CRC_TEST(v)   (((v) << 11) & BM_OCOTP_CTRL_CRC_TEST)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_CRC_TEST(v)   BF_CS1(OCOTP_CTRL, CRC_TEST, v)
#endif

/* --- Register HW_OCOTP_CTRL, field RELOAD_SHADOWS */

#define BP_OCOTP_CTRL_RELOAD_SHADOWS      10
#define BM_OCOTP_CTRL_RELOAD_SHADOWS      0x00000400

#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v)   (((v) << 10) & BM_OCOTP_CTRL_RELOAD_SHADOWS)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_RELOAD_SHADOWS(v)   BF_CS1(OCOTP_CTRL, RELOAD_SHADOWS, v)
#endif

/* --- Register HW_OCOTP_CTRL, field ERROR */

#define BP_OCOTP_CTRL_ERROR      9
#define BM_OCOTP_CTRL_ERROR      0x00000200

#define BF_OCOTP_CTRL_ERROR(v)   (((v) << 9) & BM_OCOTP_CTRL_ERROR)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_ERROR(v)   BF_CS1(OCOTP_CTRL, ERROR, v)
#endif

/* --- Register HW_OCOTP_CTRL, field BUSY */

#define BP_OCOTP_CTRL_BUSY      8
#define BM_OCOTP_CTRL_BUSY      0x00000100

#define BF_OCOTP_CTRL_BUSY(v)   (((v) << 8) & BM_OCOTP_CTRL_BUSY)
/* --- Register HW_OCOTP_CTRL, field RSVD0 */

#define BP_OCOTP_CTRL_RSVD0      7
#define BM_OCOTP_CTRL_RSVD0      0x00000080

#define BF_OCOTP_CTRL_RSVD0(v)   (((v) << 7) & BM_OCOTP_CTRL_RSVD0)
/* --- Register HW_OCOTP_CTRL, field ADDR */

#define BP_OCOTP_CTRL_ADDR      0
#define BM_OCOTP_CTRL_ADDR      0x0000007F

#define BF_OCOTP_CTRL_ADDR(v)   (((v) << 0) & BM_OCOTP_CTRL_ADDR)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CTRL_ADDR(v)   BF_CS1(OCOTP_CTRL, ADDR, v)
#endif



/*
 * HW_OCOTP_TIMING - OTP Controller Timing Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned STROBE_PROG  : 12;
        unsigned RELAX        :  4;
        unsigned STROBE_READ  :  6;
        unsigned WAIT         :  6;
        unsigned RSRVD0       :  4;
    } B;
} hw_ocotp_timing_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_TIMING register
 */
//#define HW_OCOTP_TIMING_ADDR      (0x021bc010)
#define HW_OCOTP_TIMING_ADDR      (OCOTP_TIMING)


#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_TIMING           (*(volatile hw_ocotp_timing_t *) HW_OCOTP_TIMING_ADDR)
      #define HW_OCOTP_TIMING_RD()      (HW_OCOTP_TIMING.U)
      #define HW_OCOTP_TIMING_WR(v)     (HW_OCOTP_TIMING.U = (v))
      #define HW_OCOTP_TIMING_SET(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() |  (v)))
      #define HW_OCOTP_TIMING_CLR(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() & ~(v)))
      #define HW_OCOTP_TIMING_TOG(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() ^  (v)))
   #else 
      #define HW_OCOTP_TIMING_RD()      (_rbase->mem32_read(HW_OCOTP_TIMING_ADDR))
      #define HW_OCOTP_TIMING_WR(v)     (_rbase->mem32_write(HW_OCOTP_TIMING_ADDR,(v)))
      #define HW_OCOTP_TIMING_SET(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() |  (v)))
      #define HW_OCOTP_TIMING_CLR(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() & ~(v)))
      #define HW_OCOTP_TIMING_TOG(v)    (HW_OCOTP_TIMING_WR(HW_OCOTP_TIMING_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_TIMING bitfields
 */
/* --- Register HW_OCOTP_TIMING, field RSRVD0 */

#define BP_OCOTP_TIMING_RSRVD0      28
#define BM_OCOTP_TIMING_RSRVD0      0xF0000000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_TIMING_RSRVD0(v)   ((((reg32_t) v) << 28) & BM_OCOTP_TIMING_RSRVD0)
#else
#define BF_OCOTP_TIMING_RSRVD0(v)   (((v) << 28) & BM_OCOTP_TIMING_RSRVD0)
#endif
/* --- Register HW_OCOTP_TIMING, field WAIT */

#define BP_OCOTP_TIMING_WAIT      22
#define BM_OCOTP_TIMING_WAIT      0x0FC00000

#define BF_OCOTP_TIMING_WAIT(v)   (((v) << 22) & BM_OCOTP_TIMING_WAIT)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_TIMING_WAIT(v)   BF_CS1(OCOTP_TIMING, WAIT, v)
#endif

/* --- Register HW_OCOTP_TIMING, field STROBE_READ */

#define BP_OCOTP_TIMING_STROBE_READ      16
#define BM_OCOTP_TIMING_STROBE_READ      0x003F0000

#define BF_OCOTP_TIMING_STROBE_READ(v)   (((v) << 16) & BM_OCOTP_TIMING_STROBE_READ)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_TIMING_STROBE_READ(v)   BF_CS1(OCOTP_TIMING, STROBE_READ, v)
#endif

/* --- Register HW_OCOTP_TIMING, field RELAX */

#define BP_OCOTP_TIMING_RELAX      12
#define BM_OCOTP_TIMING_RELAX      0x0000F000

#define BF_OCOTP_TIMING_RELAX(v)   (((v) << 12) & BM_OCOTP_TIMING_RELAX)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_TIMING_RELAX(v)   BF_CS1(OCOTP_TIMING, RELAX, v)
#endif

/* --- Register HW_OCOTP_TIMING, field STROBE_PROG */

#define BP_OCOTP_TIMING_STROBE_PROG      0
#define BM_OCOTP_TIMING_STROBE_PROG      0x00000FFF

#define BF_OCOTP_TIMING_STROBE_PROG(v)   (((v) << 0) & BM_OCOTP_TIMING_STROBE_PROG)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_TIMING_STROBE_PROG(v)   BF_CS1(OCOTP_TIMING, STROBE_PROG, v)
#endif



/*
 * HW_OCOTP_DATA - OTP Controller Write Data Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned DATA  : 32;
    } B;
} hw_ocotp_data_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_DATA register
 */
//#define HW_OCOTP_DATA_ADDR      (0x021bc020)
#define HW_OCOTP_DATA_ADDR      (OCOTP_DATA)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_DATA           (*(volatile hw_ocotp_data_t *) HW_OCOTP_DATA_ADDR)
      #define HW_OCOTP_DATA_RD()      (HW_OCOTP_DATA.U)
      #define HW_OCOTP_DATA_WR(v)     (HW_OCOTP_DATA.U = (v))
      #define HW_OCOTP_DATA_SET(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() |  (v)))
      #define HW_OCOTP_DATA_CLR(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() & ~(v)))
      #define HW_OCOTP_DATA_TOG(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() ^  (v)))
   #else 
      #define HW_OCOTP_DATA_RD()      (_rbase->mem32_read(HW_OCOTP_DATA_ADDR))
      #define HW_OCOTP_DATA_WR(v)     (_rbase->mem32_write(HW_OCOTP_DATA_ADDR,(v)))
      #define HW_OCOTP_DATA_SET(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() |  (v)))
      #define HW_OCOTP_DATA_CLR(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() & ~(v)))
      #define HW_OCOTP_DATA_TOG(v)    (HW_OCOTP_DATA_WR(HW_OCOTP_DATA_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_DATA bitfields
 */
/* --- Register HW_OCOTP_DATA, field DATA */

#define BP_OCOTP_DATA_DATA      0
#define BM_OCOTP_DATA_DATA      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_DATA_DATA(v)   ((reg32_t) v)
#else
#define BF_OCOTP_DATA_DATA(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_DATA_DATA(v)   (HW_OCOTP_DATA.B.DATA = (v))
#endif



/*
 * HW_OCOTP_READ_CTRL - OTP Controller Write Data Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned READ_FUSE  :  1;
        unsigned RSVD0      : 31;
    } B;
} hw_ocotp_read_ctrl_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_READ_CTRL register
 */
//#define HW_OCOTP_READ_CTRL_ADDR      (0x021bc030)
#define HW_OCOTP_READ_CTRL_ADDR      (OCOTP_READ_CTRL)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_READ_CTRL           (*(volatile hw_ocotp_read_ctrl_t *) HW_OCOTP_READ_CTRL_ADDR)
      #define HW_OCOTP_READ_CTRL_RD()      (HW_OCOTP_READ_CTRL.U)
      #define HW_OCOTP_READ_CTRL_WR(v)     (HW_OCOTP_READ_CTRL.U = (v))
      #define HW_OCOTP_READ_CTRL_SET(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() |  (v)))
      #define HW_OCOTP_READ_CTRL_CLR(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() & ~(v)))
      #define HW_OCOTP_READ_CTRL_TOG(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() ^  (v)))
   #else 
      #define HW_OCOTP_READ_CTRL_RD()      (_rbase->mem32_read(HW_OCOTP_READ_CTRL_ADDR))
      #define HW_OCOTP_READ_CTRL_WR(v)     (_rbase->mem32_write(HW_OCOTP_READ_CTRL_ADDR,(v)))
      #define HW_OCOTP_READ_CTRL_SET(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() |  (v)))
      #define HW_OCOTP_READ_CTRL_CLR(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() & ~(v)))
      #define HW_OCOTP_READ_CTRL_TOG(v)    (HW_OCOTP_READ_CTRL_WR(HW_OCOTP_READ_CTRL_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_READ_CTRL bitfields
 */
/* --- Register HW_OCOTP_READ_CTRL, field RSVD0 */

#define BP_OCOTP_READ_CTRL_RSVD0      1
#define BM_OCOTP_READ_CTRL_RSVD0      0xFFFFFFFE

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_READ_CTRL_RSVD0(v)   ((((reg32_t) v) << 1) & BM_OCOTP_READ_CTRL_RSVD0)
#else
#define BF_OCOTP_READ_CTRL_RSVD0(v)   (((v) << 1) & BM_OCOTP_READ_CTRL_RSVD0)
#endif
/* --- Register HW_OCOTP_READ_CTRL, field READ_FUSE */

#define BP_OCOTP_READ_CTRL_READ_FUSE      0
#define BM_OCOTP_READ_CTRL_READ_FUSE      0x00000001

#define BF_OCOTP_READ_CTRL_READ_FUSE(v)   (((v) << 0) & BM_OCOTP_READ_CTRL_READ_FUSE)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_READ_CTRL_READ_FUSE(v)   BF_CS1(OCOTP_READ_CTRL, READ_FUSE, v)
#endif



/*
 * HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned DATA  : 32;
    } B;
} hw_ocotp_read_fuse_data_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_READ_FUSE_DATA register
 */
//#define HW_OCOTP_READ_FUSE_DATA_ADDR      (0x021bc040)
#define HW_OCOTP_READ_FUSE_DATA_ADDR      (OCOTP_READ_FUSE_DATA)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_READ_FUSE_DATA           (*(volatile hw_ocotp_read_fuse_data_t *) HW_OCOTP_READ_FUSE_DATA_ADDR)
      #define HW_OCOTP_READ_FUSE_DATA_RD()      (HW_OCOTP_READ_FUSE_DATA.U)
      #define HW_OCOTP_READ_FUSE_DATA_WR(v)     (HW_OCOTP_READ_FUSE_DATA.U = (v))
      #define HW_OCOTP_READ_FUSE_DATA_SET(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() |  (v)))
      #define HW_OCOTP_READ_FUSE_DATA_CLR(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() & ~(v)))
      #define HW_OCOTP_READ_FUSE_DATA_TOG(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() ^  (v)))
   #else 
      #define HW_OCOTP_READ_FUSE_DATA_RD()      (_rbase->mem32_read(HW_OCOTP_READ_FUSE_DATA_ADDR))
      #define HW_OCOTP_READ_FUSE_DATA_WR(v)     (_rbase->mem32_write(HW_OCOTP_READ_FUSE_DATA_ADDR,(v)))
      #define HW_OCOTP_READ_FUSE_DATA_SET(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() |  (v)))
      #define HW_OCOTP_READ_FUSE_DATA_CLR(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() & ~(v)))
      #define HW_OCOTP_READ_FUSE_DATA_TOG(v)    (HW_OCOTP_READ_FUSE_DATA_WR(HW_OCOTP_READ_FUSE_DATA_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_READ_FUSE_DATA bitfields
 */
/* --- Register HW_OCOTP_READ_FUSE_DATA, field DATA */

#define BP_OCOTP_READ_FUSE_DATA_DATA      0
#define BM_OCOTP_READ_FUSE_DATA_DATA      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_READ_FUSE_DATA_DATA(v)   ((reg32_t) v)
#else
#define BF_OCOTP_READ_FUSE_DATA_DATA(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_READ_FUSE_DATA_DATA(v)   (HW_OCOTP_READ_FUSE_DATA.B.DATA = (v))
#endif



/*
 * HW_OCOTP_SW_STICKY - Sticky bit Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BLOCK_DTCP_KEY      :  1;
        unsigned SRK_REVOKE_LOCK     :  1;
        unsigned FIELD_RETURN_LOCK   :  1;
        unsigned BLOCK_ROM_PART      :  1;
        unsigned JTAG_BLOCK_RELEASE  :  1;
        unsigned RSVD0               : 27;
    } B;
} hw_ocotp_sw_sticky_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_SW_STICKY register
 */
//#define HW_OCOTP_SW_STICKY_ADDR      (0x021bc050)
#define HW_OCOTP_SW_STICKY_ADDR      (OCOTP_SW_STICKY)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_SW_STICKY           (*(volatile hw_ocotp_sw_sticky_t *) HW_OCOTP_SW_STICKY_ADDR)
      #define HW_OCOTP_SW_STICKY_RD()      (HW_OCOTP_SW_STICKY.U)
      #define HW_OCOTP_SW_STICKY_WR(v)     (HW_OCOTP_SW_STICKY.U = (v))
      #define HW_OCOTP_SW_STICKY_SET(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() |  (v)))
      #define HW_OCOTP_SW_STICKY_CLR(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() & ~(v)))
      #define HW_OCOTP_SW_STICKY_TOG(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() ^  (v)))
   #else 
      #define HW_OCOTP_SW_STICKY_RD()      (_rbase->mem32_read(HW_OCOTP_SW_STICKY_ADDR))
      #define HW_OCOTP_SW_STICKY_WR(v)     (_rbase->mem32_write(HW_OCOTP_SW_STICKY_ADDR,(v)))
      #define HW_OCOTP_SW_STICKY_SET(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() |  (v)))
      #define HW_OCOTP_SW_STICKY_CLR(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() & ~(v)))
      #define HW_OCOTP_SW_STICKY_TOG(v)    (HW_OCOTP_SW_STICKY_WR(HW_OCOTP_SW_STICKY_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_SW_STICKY bitfields
 */
/* --- Register HW_OCOTP_SW_STICKY, field RSVD0 */

#define BP_OCOTP_SW_STICKY_RSVD0      5
#define BM_OCOTP_SW_STICKY_RSVD0      0xFFFFFFE0

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SW_STICKY_RSVD0(v)   ((((reg32_t) v) << 5) & BM_OCOTP_SW_STICKY_RSVD0)
#else
#define BF_OCOTP_SW_STICKY_RSVD0(v)   (((v) << 5) & BM_OCOTP_SW_STICKY_RSVD0)
#endif
/* --- Register HW_OCOTP_SW_STICKY, field JTAG_BLOCK_RELEASE */

#define BP_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE      4
#define BM_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE      0x00000010

#define BF_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(v)   (((v) << 4) & BM_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(v)   BF_CS1(OCOTP_SW_STICKY, JTAG_BLOCK_RELEASE, v)
#endif

/* --- Register HW_OCOTP_SW_STICKY, field BLOCK_ROM_PART */

#define BP_OCOTP_SW_STICKY_BLOCK_ROM_PART      3
#define BM_OCOTP_SW_STICKY_BLOCK_ROM_PART      0x00000008

#define BF_OCOTP_SW_STICKY_BLOCK_ROM_PART(v)   (((v) << 3) & BM_OCOTP_SW_STICKY_BLOCK_ROM_PART)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SW_STICKY_BLOCK_ROM_PART(v)   BF_CS1(OCOTP_SW_STICKY, BLOCK_ROM_PART, v)
#endif

/* --- Register HW_OCOTP_SW_STICKY, field FIELD_RETURN_LOCK */

#define BP_OCOTP_SW_STICKY_FIELD_RETURN_LOCK      2
#define BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK      0x00000004

#define BF_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(v)   (((v) << 2) & BM_OCOTP_SW_STICKY_FIELD_RETURN_LOCK)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(v)   BF_CS1(OCOTP_SW_STICKY, FIELD_RETURN_LOCK, v)
#endif

/* --- Register HW_OCOTP_SW_STICKY, field SRK_REVOKE_LOCK */

#define BP_OCOTP_SW_STICKY_SRK_REVOKE_LOCK      1
#define BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK      0x00000002

#define BF_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(v)   (((v) << 1) & BM_OCOTP_SW_STICKY_SRK_REVOKE_LOCK)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(v)   BF_CS1(OCOTP_SW_STICKY, SRK_REVOKE_LOCK, v)
#endif

/* --- Register HW_OCOTP_SW_STICKY, field BLOCK_DTCP_KEY */

#define BP_OCOTP_SW_STICKY_BLOCK_DTCP_KEY      0
#define BM_OCOTP_SW_STICKY_BLOCK_DTCP_KEY      0x00000001

#define BF_OCOTP_SW_STICKY_BLOCK_DTCP_KEY(v)   (((v) << 0) & BM_OCOTP_SW_STICKY_BLOCK_DTCP_KEY)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SW_STICKY_BLOCK_DTCP_KEY(v)   BF_CS1(OCOTP_SW_STICKY, BLOCK_DTCP_KEY, v)
#endif



/*
 * HW_OCOTP_SCS - Software Controllable Signals Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned HAB_JDE  :  1;
        unsigned SPARE    : 30;
        unsigned LOCK     :  1;
    } B;
} hw_ocotp_scs_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_SCS register
 */
//#define HW_OCOTP_SCS_ADDR      (0x021bc060)
//#define HW_OCOTP_SCS_SET_ADDR  (0x021bc064)
//#define HW_OCOTP_SCS_CLR_ADDR  (0x021bc068)
//#define HW_OCOTP_SCS_TOG_ADDR  (0x021bc06c)
#define HW_OCOTP_SCS_ADDR      (OCOTP_SCS)
#define HW_OCOTP_SCS_SET_ADDR  (OCOTP_SCS_SET)
#define HW_OCOTP_SCS_CLR_ADDR  (OCOTP_SCS_CLR)
#define HW_OCOTP_SCS_TOG_ADDR  (OCOTP_SCS_TOG)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_SCS           (*(volatile hw_ocotp_scs_t *) HW_OCOTP_SCS_ADDR)
      #define HW_OCOTP_SCS_RD()      (HW_OCOTP_SCS.U)
      #define HW_OCOTP_SCS_WR(v)     (HW_OCOTP_SCS.U = (v))
      #define HW_OCOTP_SCS_SET(v)    ((*(volatile reg32_t *) HW_OCOTP_SCS_SET_ADDR) = (v))
      #define HW_OCOTP_SCS_CLR(v)    ((*(volatile reg32_t *) HW_OCOTP_SCS_CLR_ADDR) = (v))
      #define HW_OCOTP_SCS_TOG(v)    ((*(volatile reg32_t *) HW_OCOTP_SCS_TOG_ADDR) = (v))
   #else 
      #define HW_OCOTP_SCS_RD()      (_rbase->mem32_read(HW_OCOTP_SCS_ADDR))
      #define HW_OCOTP_SCS_WR(v)     (_rbase->mem32_write(HW_OCOTP_SCS_ADDR,(v)))
      #define HW_OCOTP_SCS_SET(v)    (_rbase->mem32_write(HW_OCOTP_SCS_SET_ADDR,(v)))
      #define HW_OCOTP_SCS_CLR(v)    (_rbase->mem32_write(HW_OCOTP_SCS_CLR_ADDR,(v)))
      #define HW_OCOTP_SCS_TOG(v)    (_rbase->mem32_write(HW_OCOTP_SCS_TOG_ADDR,(v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_SCS bitfields
 */
/* --- Register HW_OCOTP_SCS, field LOCK */

#define BP_OCOTP_SCS_LOCK      31
#define BM_OCOTP_SCS_LOCK      0x80000000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SCS_LOCK(v)   ((((reg32_t) v) << 31) & BM_OCOTP_SCS_LOCK)
#else
#define BF_OCOTP_SCS_LOCK(v)   (((v) << 31) & BM_OCOTP_SCS_LOCK)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SCS_LOCK(v)   BF_CS1(OCOTP_SCS, LOCK, v)
#endif

/* --- Register HW_OCOTP_SCS, field SPARE */

#define BP_OCOTP_SCS_SPARE      1
#define BM_OCOTP_SCS_SPARE      0x7FFFFFFE

#define BF_OCOTP_SCS_SPARE(v)   (((v) << 1) & BM_OCOTP_SCS_SPARE)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SCS_SPARE(v)   BF_CS1(OCOTP_SCS, SPARE, v)
#endif

/* --- Register HW_OCOTP_SCS, field HAB_JDE */

#define BP_OCOTP_SCS_HAB_JDE      0
#define BM_OCOTP_SCS_HAB_JDE      0x00000001

#define BF_OCOTP_SCS_HAB_JDE(v)   (((v) << 0) & BM_OCOTP_SCS_HAB_JDE)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SCS_HAB_JDE(v)   BF_CS1(OCOTP_SCS, HAB_JDE, v)
#endif



/*
 * HW_OCOTP_CRC_ADDR - OTP Controller CRC test address
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned DATA_START_ADDR  :  8;
        unsigned DATA_END_ADDR    :  8;
        unsigned CRC_ADDR         :  3;
        unsigned RSVD0            : 13;
    } B;
} hw_ocotp_crc_addr_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_CRC_ADDR register
 */
//#define HW_OCOTP_CRC_ADDR_ADDR      (0x021bc070)
#define HW_OCOTP_CRC_ADDR_ADDR      (OCOTP_CRC_ADDR)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_CRC_ADDR           (*(volatile hw_ocotp_crc_addr_t *) HW_OCOTP_CRC_ADDR_ADDR)
      #define HW_OCOTP_CRC_ADDR_RD()      (HW_OCOTP_CRC_ADDR.U)
      #define HW_OCOTP_CRC_ADDR_WR(v)     (HW_OCOTP_CRC_ADDR.U = (v))
      #define HW_OCOTP_CRC_ADDR_SET(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() |  (v)))
      #define HW_OCOTP_CRC_ADDR_CLR(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() & ~(v)))
      #define HW_OCOTP_CRC_ADDR_TOG(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() ^  (v)))
   #else 
      #define HW_OCOTP_CRC_ADDR_RD()      (_rbase->mem32_read(HW_OCOTP_CRC_ADDR_ADDR))
      #define HW_OCOTP_CRC_ADDR_WR(v)     (_rbase->mem32_write(HW_OCOTP_CRC_ADDR_ADDR,(v)))
      #define HW_OCOTP_CRC_ADDR_SET(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() |  (v)))
      #define HW_OCOTP_CRC_ADDR_CLR(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() & ~(v)))
      #define HW_OCOTP_CRC_ADDR_TOG(v)    (HW_OCOTP_CRC_ADDR_WR(HW_OCOTP_CRC_ADDR_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_CRC_ADDR bitfields
 */
/* --- Register HW_OCOTP_CRC_ADDR, field RSVD0 */

#define BP_OCOTP_CRC_ADDR_RSVD0      19
#define BM_OCOTP_CRC_ADDR_RSVD0      0xFFF80000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_CRC_ADDR_RSVD0(v)   ((((reg32_t) v) << 19) & BM_OCOTP_CRC_ADDR_RSVD0)
#else
#define BF_OCOTP_CRC_ADDR_RSVD0(v)   (((v) << 19) & BM_OCOTP_CRC_ADDR_RSVD0)
#endif
/* --- Register HW_OCOTP_CRC_ADDR, field CRC_ADDR */

#define BP_OCOTP_CRC_ADDR_CRC_ADDR      16
#define BM_OCOTP_CRC_ADDR_CRC_ADDR      0x00070000

#define BF_OCOTP_CRC_ADDR_CRC_ADDR(v)   (((v) << 16) & BM_OCOTP_CRC_ADDR_CRC_ADDR)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CRC_ADDR_CRC_ADDR(v)   BF_CS1(OCOTP_CRC_ADDR, CRC_ADDR, v)
#endif

/* --- Register HW_OCOTP_CRC_ADDR, field DATA_END_ADDR */

#define BP_OCOTP_CRC_ADDR_DATA_END_ADDR      8
#define BM_OCOTP_CRC_ADDR_DATA_END_ADDR      0x0000FF00

#define BF_OCOTP_CRC_ADDR_DATA_END_ADDR(v)   (((v) << 8) & BM_OCOTP_CRC_ADDR_DATA_END_ADDR)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CRC_ADDR_DATA_END_ADDR(v)   (HW_OCOTP_CRC_ADDR.B.DATA_END_ADDR = (v))
#endif

/* --- Register HW_OCOTP_CRC_ADDR, field DATA_START_ADDR */

#define BP_OCOTP_CRC_ADDR_DATA_START_ADDR      0
#define BM_OCOTP_CRC_ADDR_DATA_START_ADDR      0x000000FF

#define BF_OCOTP_CRC_ADDR_DATA_START_ADDR(v)   (((v) << 0) & BM_OCOTP_CRC_ADDR_DATA_START_ADDR)
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CRC_ADDR_DATA_START_ADDR(v)   (HW_OCOTP_CRC_ADDR.B.DATA_START_ADDR = (v))
#endif



/*
 * HW_OCOTP_CRC_VALUE - OTP Controller CRC Value Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned DATA  : 32;
    } B;
} hw_ocotp_crc_value_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_CRC_VALUE register
 */
//#define HW_OCOTP_CRC_VALUE_ADDR      (0x021bc080)
#define HW_OCOTP_CRC_VALUE_ADDR      (OCOTP_CRC_VALUE)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_CRC_VALUE           (*(volatile hw_ocotp_crc_value_t *) HW_OCOTP_CRC_VALUE_ADDR)
      #define HW_OCOTP_CRC_VALUE_RD()      (HW_OCOTP_CRC_VALUE.U)
      #define HW_OCOTP_CRC_VALUE_WR(v)     (HW_OCOTP_CRC_VALUE.U = (v))
      #define HW_OCOTP_CRC_VALUE_SET(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() |  (v)))
      #define HW_OCOTP_CRC_VALUE_CLR(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() & ~(v)))
      #define HW_OCOTP_CRC_VALUE_TOG(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() ^  (v)))
   #else 
      #define HW_OCOTP_CRC_VALUE_RD()      (_rbase->mem32_read(HW_OCOTP_CRC_VALUE_ADDR))
      #define HW_OCOTP_CRC_VALUE_WR(v)     (_rbase->mem32_write(HW_OCOTP_CRC_VALUE_ADDR,(v)))
      #define HW_OCOTP_CRC_VALUE_SET(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() |  (v)))
      #define HW_OCOTP_CRC_VALUE_CLR(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() & ~(v)))
      #define HW_OCOTP_CRC_VALUE_TOG(v)    (HW_OCOTP_CRC_VALUE_WR(HW_OCOTP_CRC_VALUE_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_CRC_VALUE bitfields
 */
/* --- Register HW_OCOTP_CRC_VALUE, field DATA */

#define BP_OCOTP_CRC_VALUE_DATA      0
#define BM_OCOTP_CRC_VALUE_DATA      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_CRC_VALUE_DATA(v)   ((reg32_t) v)
#else
#define BF_OCOTP_CRC_VALUE_DATA(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CRC_VALUE_DATA(v)   (HW_OCOTP_CRC_VALUE.B.DATA = (v))
#endif



/*
 * HW_OCOTP_VERSION - OTP Controller Version Register
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned STEP   : 16;
        unsigned MINOR  :  8;
        unsigned MAJOR  :  8;
    } B;
} hw_ocotp_version_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_VERSION register
 */
//#define HW_OCOTP_VERSION_ADDR      (0x021bc090)
#define HW_OCOTP_VERSION_ADDR      (OCOTP_VERSION)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_VERSION           (*(volatile hw_ocotp_version_t *) HW_OCOTP_VERSION_ADDR)
      #define HW_OCOTP_VERSION_RD()      (HW_OCOTP_VERSION.U)
   #else 
      #define HW_OCOTP_VERSION_RD()      (_rbase->mem32_read(HW_OCOTP_VERSION_ADDR))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_VERSION bitfields
 */
/* --- Register HW_OCOTP_VERSION, field MAJOR */

#define BP_OCOTP_VERSION_MAJOR      24
#define BM_OCOTP_VERSION_MAJOR      0xFF000000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_VERSION_MAJOR(v)   ((((reg32_t) v) << 24) & BM_OCOTP_VERSION_MAJOR)
#else
#define BF_OCOTP_VERSION_MAJOR(v)   (((v) << 24) & BM_OCOTP_VERSION_MAJOR)
#endif
/* --- Register HW_OCOTP_VERSION, field MINOR */

#define BP_OCOTP_VERSION_MINOR      16
#define BM_OCOTP_VERSION_MINOR      0x00FF0000

#define BF_OCOTP_VERSION_MINOR(v)   (((v) << 16) & BM_OCOTP_VERSION_MINOR)
/* --- Register HW_OCOTP_VERSION, field STEP */

#define BP_OCOTP_VERSION_STEP      0
#define BM_OCOTP_VERSION_STEP      0x0000FFFF

#define BF_OCOTP_VERSION_STEP(v)   (((v) << 0) & BM_OCOTP_VERSION_STEP)


/*
 * HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned TESTER          :  2;
        unsigned BOOT_CFG        :  2;
        unsigned MEM_TRIM        :  2;
        unsigned SJC_RESP        :  1;
        unsigned RSVD0           :  1;
        unsigned MAC_ADDR        :  2;
        unsigned GP1             :  2;
        unsigned GP2             :  2;
        unsigned SRK             :  1;
        unsigned RSVD1           :  1;
        unsigned DTCP_KEY        :  1;
        unsigned OTPMK           :  1;
        unsigned ANALOG          :  2;
        unsigned HDCP_KSV        :  1;
        unsigned HDCP_KEYS       :  1;
        unsigned SATA_CONF       :  1;
        unsigned DTCP_DEV_CERT   :  1;
        unsigned RSVD2           :  1;
        unsigned PIN             :  1;
        unsigned CRC_GP_LO_LOCK  :  2;
        unsigned CRC_GP_HI_LOCK  :  2;
        unsigned UNALLOCATED     :  2;
    } B;
} hw_ocotp_lock_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_LOCK register
 */
//#define HW_OCOTP_LOCK_ADDR      (0x021bc400)
#define HW_OCOTP_LOCK_ADDR      (OCOTP_LOCK)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_LOCK           (*(volatile hw_ocotp_lock_t *) HW_OCOTP_LOCK_ADDR)
      #define HW_OCOTP_LOCK_RD()      (HW_OCOTP_LOCK.U)
   #else 
      #define HW_OCOTP_LOCK_RD()      (_rbase->mem32_read(HW_OCOTP_LOCK_ADDR))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_LOCK bitfields
 */
/* --- Register HW_OCOTP_LOCK, field UNALLOCATED */

#define BP_OCOTP_LOCK_UNALLOCATED      30
#define BM_OCOTP_LOCK_UNALLOCATED      0xC0000000

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_LOCK_UNALLOCATED(v)   ((((reg32_t) v) << 30) & BM_OCOTP_LOCK_UNALLOCATED)
#else
#define BF_OCOTP_LOCK_UNALLOCATED(v)   (((v) << 30) & BM_OCOTP_LOCK_UNALLOCATED)
#endif
/* --- Register HW_OCOTP_LOCK, field CRC_GP_HI_LOCK */

#define BP_OCOTP_LOCK_CRC_GP_HI_LOCK      28
#define BM_OCOTP_LOCK_CRC_GP_HI_LOCK      0x30000000

#define BF_OCOTP_LOCK_CRC_GP_HI_LOCK(v)   (((v) << 28) & BM_OCOTP_LOCK_CRC_GP_HI_LOCK)
/* --- Register HW_OCOTP_LOCK, field CRC_GP_LO_LOCK */

#define BP_OCOTP_LOCK_CRC_GP_LO_LOCK      26
#define BM_OCOTP_LOCK_CRC_GP_LO_LOCK      0x0C000000

#define BF_OCOTP_LOCK_CRC_GP_LO_LOCK(v)   (((v) << 26) & BM_OCOTP_LOCK_CRC_GP_LO_LOCK)
/* --- Register HW_OCOTP_LOCK, field PIN */

#define BP_OCOTP_LOCK_PIN      25
#define BM_OCOTP_LOCK_PIN      0x02000000

#define BF_OCOTP_LOCK_PIN(v)   (((v) << 25) & BM_OCOTP_LOCK_PIN)
/* --- Register HW_OCOTP_LOCK, field RSVD2 */

#define BP_OCOTP_LOCK_RSVD2      24
#define BM_OCOTP_LOCK_RSVD2      0x01000000

#define BF_OCOTP_LOCK_RSVD2(v)   (((v) << 24) & BM_OCOTP_LOCK_RSVD2)
/* --- Register HW_OCOTP_LOCK, field DTCP_DEV_CERT */

#define BP_OCOTP_LOCK_DTCP_DEV_CERT      23
#define BM_OCOTP_LOCK_DTCP_DEV_CERT      0x00800000

#define BF_OCOTP_LOCK_DTCP_DEV_CERT(v)   (((v) << 23) & BM_OCOTP_LOCK_DTCP_DEV_CERT)
/* --- Register HW_OCOTP_LOCK, field SATA_CONF */

#define BP_OCOTP_LOCK_SATA_CONF      22
#define BM_OCOTP_LOCK_SATA_CONF      0x00400000

#define BF_OCOTP_LOCK_SATA_CONF(v)   (((v) << 22) & BM_OCOTP_LOCK_SATA_CONF)
/* --- Register HW_OCOTP_LOCK, field HDCP_KEYS */

#define BP_OCOTP_LOCK_HDCP_KEYS      21
#define BM_OCOTP_LOCK_HDCP_KEYS      0x00200000

#define BF_OCOTP_LOCK_HDCP_KEYS(v)   (((v) << 21) & BM_OCOTP_LOCK_HDCP_KEYS)
/* --- Register HW_OCOTP_LOCK, field HDCP_KSV */

#define BP_OCOTP_LOCK_HDCP_KSV      20
#define BM_OCOTP_LOCK_HDCP_KSV      0x00100000

#define BF_OCOTP_LOCK_HDCP_KSV(v)   (((v) << 20) & BM_OCOTP_LOCK_HDCP_KSV)
/* --- Register HW_OCOTP_LOCK, field ANALOG */

#define BP_OCOTP_LOCK_ANALOG      18
#define BM_OCOTP_LOCK_ANALOG      0x000C0000

#define BF_OCOTP_LOCK_ANALOG(v)   (((v) << 18) & BM_OCOTP_LOCK_ANALOG)
/* --- Register HW_OCOTP_LOCK, field OTPMK */

#define BP_OCOTP_LOCK_OTPMK      17
#define BM_OCOTP_LOCK_OTPMK      0x00020000

#define BF_OCOTP_LOCK_OTPMK(v)   (((v) << 17) & BM_OCOTP_LOCK_OTPMK)
/* --- Register HW_OCOTP_LOCK, field DTCP_KEY */

#define BP_OCOTP_LOCK_DTCP_KEY      16
#define BM_OCOTP_LOCK_DTCP_KEY      0x00010000

#define BF_OCOTP_LOCK_DTCP_KEY(v)   (((v) << 16) & BM_OCOTP_LOCK_DTCP_KEY)
/* --- Register HW_OCOTP_LOCK, field RSVD1 */

#define BP_OCOTP_LOCK_RSVD1      15
#define BM_OCOTP_LOCK_RSVD1      0x00008000

#define BF_OCOTP_LOCK_RSVD1(v)   (((v) << 15) & BM_OCOTP_LOCK_RSVD1)
/* --- Register HW_OCOTP_LOCK, field SRK */

#define BP_OCOTP_LOCK_SRK      14
#define BM_OCOTP_LOCK_SRK      0x00004000

#define BF_OCOTP_LOCK_SRK(v)   (((v) << 14) & BM_OCOTP_LOCK_SRK)
/* --- Register HW_OCOTP_LOCK, field GP2 */

#define BP_OCOTP_LOCK_GP2      12
#define BM_OCOTP_LOCK_GP2      0x00003000

#define BF_OCOTP_LOCK_GP2(v)   (((v) << 12) & BM_OCOTP_LOCK_GP2)
/* --- Register HW_OCOTP_LOCK, field GP1 */

#define BP_OCOTP_LOCK_GP1      10
#define BM_OCOTP_LOCK_GP1      0x00000C00

#define BF_OCOTP_LOCK_GP1(v)   (((v) << 10) & BM_OCOTP_LOCK_GP1)
/* --- Register HW_OCOTP_LOCK, field MAC_ADDR */

#define BP_OCOTP_LOCK_MAC_ADDR      8
#define BM_OCOTP_LOCK_MAC_ADDR      0x00000300

#define BF_OCOTP_LOCK_MAC_ADDR(v)   (((v) << 8) & BM_OCOTP_LOCK_MAC_ADDR)
/* --- Register HW_OCOTP_LOCK, field RSVD0 */

#define BP_OCOTP_LOCK_RSVD0      7
#define BM_OCOTP_LOCK_RSVD0      0x00000080

#define BF_OCOTP_LOCK_RSVD0(v)   (((v) << 7) & BM_OCOTP_LOCK_RSVD0)
/* --- Register HW_OCOTP_LOCK, field SJC_RESP */

#define BP_OCOTP_LOCK_SJC_RESP      6
#define BM_OCOTP_LOCK_SJC_RESP      0x00000040

#define BF_OCOTP_LOCK_SJC_RESP(v)   (((v) << 6) & BM_OCOTP_LOCK_SJC_RESP)
/* --- Register HW_OCOTP_LOCK, field MEM_TRIM */

#define BP_OCOTP_LOCK_MEM_TRIM      4
#define BM_OCOTP_LOCK_MEM_TRIM      0x00000030

#define BF_OCOTP_LOCK_MEM_TRIM(v)   (((v) << 4) & BM_OCOTP_LOCK_MEM_TRIM)
/* --- Register HW_OCOTP_LOCK, field BOOT_CFG */

#define BP_OCOTP_LOCK_BOOT_CFG      2
#define BM_OCOTP_LOCK_BOOT_CFG      0x0000000C

#define BF_OCOTP_LOCK_BOOT_CFG(v)   (((v) << 2) & BM_OCOTP_LOCK_BOOT_CFG)
/* --- Register HW_OCOTP_LOCK, field TESTER */

#define BP_OCOTP_LOCK_TESTER      0
#define BM_OCOTP_LOCK_TESTER      0x00000003

#define BF_OCOTP_LOCK_TESTER(v)   (((v) << 0) & BM_OCOTP_LOCK_TESTER)


/*
 *  multi-register-define name HW_OCOTP_CFGn
 *              base 0x00000410
 *              count 7
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_cfgn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_CFGn multi-register
     */
    #define HW_OCOTP_CFGn_COUNT        7
    //#define HW_OCOTP_CFGn_ADDR(n)      (0x021bc410 + ((n) * 0x10))
    #define HW_OCOTP_CFGn_ADDR(n)      (OCOTP_CFG0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_CFGn(n)           (*(volatile hw_ocotp_cfgn_t *) HW_OCOTP_CFGn_ADDR(n))
    #define HW_OCOTP_CFGn_RD(n)        (HW_OCOTP_CFGn(n).U)
    #define HW_OCOTP_CFGn_WR(n, v)     (HW_OCOTP_CFGn(n).U = (v))
    #define HW_OCOTP_CFGn_SET(n, v)    (HW_OCOTP_CFGn_WR(n, HW_OCOTP_CFGn_RD(n) |  (v)))
    #define HW_OCOTP_CFGn_CLR(n, v)    (HW_OCOTP_CFGn_WR(n, HW_OCOTP_CFGn_RD(n) & ~(v)))
    #define HW_OCOTP_CFGn_TOG(n, v)    (HW_OCOTP_CFGn_WR(n, HW_OCOTP_CFGn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_CFGn multi-register bitfields
 */
/* --- Register HW_OCOTP_CFGn, field BITS */

#define BP_OCOTP_CFGn_BITS      0
#define BM_OCOTP_CFGn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_CFGn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_CFGn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CFGn_BITS(n, v)  (HW_OCOTP_CFGn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_MEMn
 *              base 0x00000480
 *              count 5
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_memn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_MEMn multi-register
     */
    #define HW_OCOTP_MEMn_COUNT        5
    //#define HW_OCOTP_MEMn_ADDR(n)      (0x021bc480 + ((n) * 0x10))
    #define HW_OCOTP_MEMn_ADDR(n)      (OCOTP_MEM0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_MEMn(n)           (*(volatile hw_ocotp_memn_t *) HW_OCOTP_MEMn_ADDR(n))
    #define HW_OCOTP_MEMn_RD(n)        (HW_OCOTP_MEMn(n).U)
    #define HW_OCOTP_MEMn_WR(n, v)     (HW_OCOTP_MEMn(n).U = (v))
    #define HW_OCOTP_MEMn_SET(n, v)    (HW_OCOTP_MEMn_WR(n, HW_OCOTP_MEMn_RD(n) |  (v)))
    #define HW_OCOTP_MEMn_CLR(n, v)    (HW_OCOTP_MEMn_WR(n, HW_OCOTP_MEMn_RD(n) & ~(v)))
    #define HW_OCOTP_MEMn_TOG(n, v)    (HW_OCOTP_MEMn_WR(n, HW_OCOTP_MEMn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_MEMn multi-register bitfields
 */
/* --- Register HW_OCOTP_MEMn, field BITS */

#define BP_OCOTP_MEMn_BITS      0
#define BM_OCOTP_MEMn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_MEMn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_MEMn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_MEMn_BITS(n, v)  (HW_OCOTP_MEMn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_ANAn
 *              base 0x000004D0
 *              count 3
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_anan_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_ANAn multi-register
     */
    #define HW_OCOTP_ANAn_COUNT        3
    //#define HW_OCOTP_ANAn_ADDR(n)      (0x021bc4d0 + ((n) * 0x10))
    #define HW_OCOTP_ANAn_ADDR(n)      (OCOTP_ANA0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_ANAn(n)           (*(volatile hw_ocotp_anan_t *) HW_OCOTP_ANAn_ADDR(n))
    #define HW_OCOTP_ANAn_RD(n)        (HW_OCOTP_ANAn(n).U)
    #define HW_OCOTP_ANAn_WR(n, v)     (HW_OCOTP_ANAn(n).U = (v))
    #define HW_OCOTP_ANAn_SET(n, v)    (HW_OCOTP_ANAn_WR(n, HW_OCOTP_ANAn_RD(n) |  (v)))
    #define HW_OCOTP_ANAn_CLR(n, v)    (HW_OCOTP_ANAn_WR(n, HW_OCOTP_ANAn_RD(n) & ~(v)))
    #define HW_OCOTP_ANAn_TOG(n, v)    (HW_OCOTP_ANAn_WR(n, HW_OCOTP_ANAn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_ANAn multi-register bitfields
 */
/* --- Register HW_OCOTP_ANAn, field BITS */

#define BP_OCOTP_ANAn_BITS      0
#define BM_OCOTP_ANAn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_ANAn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_ANAn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_ANAn_BITS(n, v)  (HW_OCOTP_ANAn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_OTPMKn
 *              base 0x00000500
 *              count 8
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_otpmkn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_OTPMKn multi-register
     */
    #define HW_OCOTP_OTPMKn_COUNT        8
    //#define HW_OCOTP_OTPMKn_ADDR(n) 	 (0x021bc500 + ((n) * 0x10))
    #define HW_OCOTP_OTPMKn_ADDR(n)      (OCOTP_OTPMK0 + ((n) * 0x10))
	
    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_OTPMKn(n)           (*(volatile hw_ocotp_otpmkn_t *) HW_OCOTP_OTPMKn_ADDR(n))
    #define HW_OCOTP_OTPMKn_RD(n)        (HW_OCOTP_OTPMKn(n).U)
    #define HW_OCOTP_OTPMKn_WR(n, v)     (HW_OCOTP_OTPMKn(n).U = (v))
    #define HW_OCOTP_OTPMKn_SET(n, v)    (HW_OCOTP_OTPMKn_WR(n, HW_OCOTP_OTPMKn_RD(n) |  (v)))
    #define HW_OCOTP_OTPMKn_CLR(n, v)    (HW_OCOTP_OTPMKn_WR(n, HW_OCOTP_OTPMKn_RD(n) & ~(v)))
    #define HW_OCOTP_OTPMKn_TOG(n, v)    (HW_OCOTP_OTPMKn_WR(n, HW_OCOTP_OTPMKn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_OTPMKn multi-register bitfields
 */
/* --- Register HW_OCOTP_OTPMKn, field BITS */

#define BP_OCOTP_OTPMKn_BITS      0
#define BM_OCOTP_OTPMKn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_OTPMKn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_OTPMKn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_OTPMKn_BITS(n, v)  (HW_OCOTP_OTPMKn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_SRKn
 *              base 0x00000580
 *              count 8
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_srkn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_SRKn multi-register
     */
    #define HW_OCOTP_SRKn_COUNT        8
    //#define HW_OCOTP_SRKn_ADDR(n)      (0x021bc580 + ((n) * 0x10))
    #define HW_OCOTP_SRKn_ADDR(n)      (OCOTP_SRK0 + ((n) * 0x10))
	
    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_SRKn(n)           (*(volatile hw_ocotp_srkn_t *) HW_OCOTP_SRKn_ADDR(n))
    #define HW_OCOTP_SRKn_RD(n)        (HW_OCOTP_SRKn(n).U)
    #define HW_OCOTP_SRKn_WR(n, v)     (HW_OCOTP_SRKn(n).U = (v))
    #define HW_OCOTP_SRKn_SET(n, v)    (HW_OCOTP_SRKn_WR(n, HW_OCOTP_SRKn_RD(n) |  (v)))
    #define HW_OCOTP_SRKn_CLR(n, v)    (HW_OCOTP_SRKn_WR(n, HW_OCOTP_SRKn_RD(n) & ~(v)))
    #define HW_OCOTP_SRKn_TOG(n, v)    (HW_OCOTP_SRKn_WR(n, HW_OCOTP_SRKn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_SRKn multi-register bitfields
 */
/* --- Register HW_OCOTP_SRKn, field BITS */

#define BP_OCOTP_SRKn_BITS      0
#define BM_OCOTP_SRKn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SRKn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_SRKn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SRKn_BITS(n, v)  (HW_OCOTP_SRKn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_SJC_RESPn
 *              base 0x00000600
 *              count 2
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_sjc_respn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_SJC_RESPn multi-register
     */
    #define HW_OCOTP_SJC_RESPn_COUNT        2
    //#define HW_OCOTP_SJC_RESPn_ADDR(n)      (0x021bc600 + ((n) * 0x10))
    #define HW_OCOTP_SJC_RESPn_ADDR(n)      (OCOTP_RESP0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_SJC_RESPn(n)           (*(volatile hw_ocotp_sjc_respn_t *) HW_OCOTP_SJC_RESPn_ADDR(n))
    #define HW_OCOTP_SJC_RESPn_RD(n)        (HW_OCOTP_SJC_RESPn(n).U)
    #define HW_OCOTP_SJC_RESPn_WR(n, v)     (HW_OCOTP_SJC_RESPn(n).U = (v))
    #define HW_OCOTP_SJC_RESPn_SET(n, v)    (HW_OCOTP_SJC_RESPn_WR(n, HW_OCOTP_SJC_RESPn_RD(n) |  (v)))
    #define HW_OCOTP_SJC_RESPn_CLR(n, v)    (HW_OCOTP_SJC_RESPn_WR(n, HW_OCOTP_SJC_RESPn_RD(n) & ~(v)))
    #define HW_OCOTP_SJC_RESPn_TOG(n, v)    (HW_OCOTP_SJC_RESPn_WR(n, HW_OCOTP_SJC_RESPn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_SJC_RESPn multi-register bitfields
 */
/* --- Register HW_OCOTP_SJC_RESPn, field BITS */

#define BP_OCOTP_SJC_RESPn_BITS      0
#define BM_OCOTP_SJC_RESPn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SJC_RESPn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_SJC_RESPn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SJC_RESPn_BITS(n, v)  (HW_OCOTP_SJC_RESPn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_MACn
 *              base 0x00000620
// *              count 2
 *              count 4   //changed for faraday
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_macn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_MACn multi-register
     */
    //#define HW_OCOTP_MACn_COUNT        2
    #define HW_OCOTP_MACn_COUNT        4     //changed for faraday by Pankaj

    //#define HW_OCOTP_MACn_ADDR(n)      (0x021bc620 + ((n) * 0x10))
    #define HW_OCOTP_MACn_ADDR(n)      (OCOTP_MAC0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_MACn(n)           (*(volatile hw_ocotp_macn_t *) HW_OCOTP_MACn_ADDR(n))
    #define HW_OCOTP_MACn_RD(n)        (HW_OCOTP_MACn(n).U)
    #define HW_OCOTP_MACn_WR(n, v)     (HW_OCOTP_MACn(n).U = (v))
    #define HW_OCOTP_MACn_SET(n, v)    (HW_OCOTP_MACn_WR(n, HW_OCOTP_MACn_RD(n) |  (v)))
    #define HW_OCOTP_MACn_CLR(n, v)    (HW_OCOTP_MACn_WR(n, HW_OCOTP_MACn_RD(n) & ~(v)))
    #define HW_OCOTP_MACn_TOG(n, v)    (HW_OCOTP_MACn_WR(n, HW_OCOTP_MACn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_MACn multi-register bitfields
 */
/* --- Register HW_OCOTP_MACn, field BITS */

#define BP_OCOTP_MACn_BITS      0
#define BM_OCOTP_MACn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_MACn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_MACn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_MACn_BITS(n, v)  (HW_OCOTP_MACn(n).B.BITS = (v))
#endif



#if 0    //perhaps HDCP is not there on faraday
/*
 *  multi-register-define name HW_OCOTP_HDCP_KSVn
 *              base 0x00000640
 *              count 2
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_hdcp_ksvn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_HDCP_KSVn multi-register
     */
    #define HW_OCOTP_HDCP_KSVn_COUNT        2
    #define HW_OCOTP_HDCP_KSVn_ADDR(n)      (0x021bc640 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_HDCP_KSVn(n)           (*(volatile hw_ocotp_hdcp_ksvn_t *) HW_OCOTP_HDCP_KSVn_ADDR(n))
    #define HW_OCOTP_HDCP_KSVn_RD(n)        (HW_OCOTP_HDCP_KSVn(n).U)
    #define HW_OCOTP_HDCP_KSVn_WR(n, v)     (HW_OCOTP_HDCP_KSVn(n).U = (v))
    #define HW_OCOTP_HDCP_KSVn_SET(n, v)    (HW_OCOTP_HDCP_KSVn_WR(n, HW_OCOTP_HDCP_KSVn_RD(n) |  (v)))
    #define HW_OCOTP_HDCP_KSVn_CLR(n, v)    (HW_OCOTP_HDCP_KSVn_WR(n, HW_OCOTP_HDCP_KSVn_RD(n) & ~(v)))
    #define HW_OCOTP_HDCP_KSVn_TOG(n, v)    (HW_OCOTP_HDCP_KSVn_WR(n, HW_OCOTP_HDCP_KSVn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_HDCP_KSVn multi-register bitfields
 */
/* --- Register HW_OCOTP_HDCP_KSVn, field BITS */

#define BP_OCOTP_HDCP_KSVn_BITS      0
#define BM_OCOTP_HDCP_KSVn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_HDCP_KSVn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_HDCP_KSVn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_HDCP_KSVn_BITS(n, v)  (HW_OCOTP_HDCP_KSVn(n).B.BITS = (v))
#endif
#endif


/*
 * HW_OCOTP_GP1 - Value of OTP Bank4 Word6 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_gp1_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_GP1 register
 */
//#define HW_OCOTP_GP1_ADDR      (0x021bc660)
#define HW_OCOTP_GP1_ADDR      (OCOTP_GP1)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_GP1           (*(volatile hw_ocotp_gp1_t *) HW_OCOTP_GP1_ADDR)
      #define HW_OCOTP_GP1_RD()      (HW_OCOTP_GP1.U)
      #define HW_OCOTP_GP1_WR(v)     (HW_OCOTP_GP1.U = (v))
      #define HW_OCOTP_GP1_SET(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() |  (v)))
      #define HW_OCOTP_GP1_CLR(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() & ~(v)))
      #define HW_OCOTP_GP1_TOG(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() ^  (v)))
   #else 
      #define HW_OCOTP_GP1_RD()      (_rbase->mem32_read(HW_OCOTP_GP1_ADDR))
      #define HW_OCOTP_GP1_WR(v)     (_rbase->mem32_write(HW_OCOTP_GP1_ADDR,(v)))
      #define HW_OCOTP_GP1_SET(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() |  (v)))
      #define HW_OCOTP_GP1_CLR(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() & ~(v)))
      #define HW_OCOTP_GP1_TOG(v)    (HW_OCOTP_GP1_WR(HW_OCOTP_GP1_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_GP1 bitfields
 */
/* --- Register HW_OCOTP_GP1, field BITS */

#define BP_OCOTP_GP1_BITS      0
#define BM_OCOTP_GP1_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_GP1_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_GP1_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_GP1_BITS(v)   (HW_OCOTP_GP1.B.BITS = (v))
#endif



/*
 * HW_OCOTP_GP2 - Value of OTP Bank4 Word7 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_gp2_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_GP2 register
 */
//#define HW_OCOTP_GP2_ADDR      (0x021bc670)
#define HW_OCOTP_GP2_ADDR      (OCOTP_GP2)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_GP2           (*(volatile hw_ocotp_gp2_t *) HW_OCOTP_GP2_ADDR)
      #define HW_OCOTP_GP2_RD()      (HW_OCOTP_GP2.U)
      #define HW_OCOTP_GP2_WR(v)     (HW_OCOTP_GP2.U = (v))
      #define HW_OCOTP_GP2_SET(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() |  (v)))
      #define HW_OCOTP_GP2_CLR(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() & ~(v)))
      #define HW_OCOTP_GP2_TOG(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() ^  (v)))
   #else 
      #define HW_OCOTP_GP2_RD()      (_rbase->mem32_read(HW_OCOTP_GP2_ADDR))
      #define HW_OCOTP_GP2_WR(v)     (_rbase->mem32_write(HW_OCOTP_GP2_ADDR,(v)))
      #define HW_OCOTP_GP2_SET(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() |  (v)))
      #define HW_OCOTP_GP2_CLR(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() & ~(v)))
      #define HW_OCOTP_GP2_TOG(v)    (HW_OCOTP_GP2_WR(HW_OCOTP_GP2_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_GP2 bitfields
 */
/* --- Register HW_OCOTP_GP2, field BITS */

#define BP_OCOTP_GP2_BITS      0
#define BM_OCOTP_GP2_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_GP2_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_GP2_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_GP2_BITS(v)   (HW_OCOTP_GP2.B.BITS = (v))
#endif


#if 0 //reserved on faraday
/*
 *  multi-register-define name HW_OCOTP_DTCP_KEYn
 *              base 0x00000680
 *              count 5
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_dtcp_keyn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_DTCP_KEYn multi-register
     */
    #define HW_OCOTP_DTCP_KEYn_COUNT        5
    #define HW_OCOTP_DTCP_KEYn_ADDR(n)      (0x021bc680 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_DTCP_KEYn(n)           (*(volatile hw_ocotp_dtcp_keyn_t *) HW_OCOTP_DTCP_KEYn_ADDR(n))
    #define HW_OCOTP_DTCP_KEYn_RD(n)        (HW_OCOTP_DTCP_KEYn(n).U)
    #define HW_OCOTP_DTCP_KEYn_WR(n, v)     (HW_OCOTP_DTCP_KEYn(n).U = (v))
    #define HW_OCOTP_DTCP_KEYn_SET(n, v)    (HW_OCOTP_DTCP_KEYn_WR(n, HW_OCOTP_DTCP_KEYn_RD(n) |  (v)))
    #define HW_OCOTP_DTCP_KEYn_CLR(n, v)    (HW_OCOTP_DTCP_KEYn_WR(n, HW_OCOTP_DTCP_KEYn_RD(n) & ~(v)))
    #define HW_OCOTP_DTCP_KEYn_TOG(n, v)    (HW_OCOTP_DTCP_KEYn_WR(n, HW_OCOTP_DTCP_KEYn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_DTCP_KEYn multi-register bitfields
 */
/* --- Register HW_OCOTP_DTCP_KEYn, field BITS */

#define BP_OCOTP_DTCP_KEYn_BITS      0
#define BM_OCOTP_DTCP_KEYn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_DTCP_KEYn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_DTCP_KEYn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_DTCP_KEYn_BITS(n, v)  (HW_OCOTP_DTCP_KEYn(n).B.BITS = (v))
#endif
#endif



#if 0 //SATA not there on faraday
/*
 * HW_OCOTP_SATA_CONF - Value of OTP Bank5 Word5 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_sata_conf_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_SATA_CONF register
 */
#define HW_OCOTP_SATA_CONF_ADDR      (0x021bc6d0)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_SATA_CONF           (*(volatile hw_ocotp_sata_conf_t *) HW_OCOTP_SATA_CONF_ADDR)
      #define HW_OCOTP_SATA_CONF_RD()      (HW_OCOTP_SATA_CONF.U)
      #define HW_OCOTP_SATA_CONF_WR(v)     (HW_OCOTP_SATA_CONF.U = (v))
      #define HW_OCOTP_SATA_CONF_SET(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() |  (v)))
      #define HW_OCOTP_SATA_CONF_CLR(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() & ~(v)))
      #define HW_OCOTP_SATA_CONF_TOG(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() ^  (v)))
   #else 
      #define HW_OCOTP_SATA_CONF_RD()      (_rbase->mem32_read(HW_OCOTP_SATA_CONF_ADDR))
      #define HW_OCOTP_SATA_CONF_WR(v)     (_rbase->mem32_write(HW_OCOTP_SATA_CONF_ADDR,(v)))
      #define HW_OCOTP_SATA_CONF_SET(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() |  (v)))
      #define HW_OCOTP_SATA_CONF_CLR(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() & ~(v)))
      #define HW_OCOTP_SATA_CONF_TOG(v)    (HW_OCOTP_SATA_CONF_WR(HW_OCOTP_SATA_CONF_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_SATA_CONF bitfields
 */
/* --- Register HW_OCOTP_SATA_CONF, field BITS */

#define BP_OCOTP_SATA_CONF_BITS      0
#define BM_OCOTP_SATA_CONF_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SATA_CONF_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_SATA_CONF_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SATA_CONF_BITS(v)   (HW_OCOTP_SATA_CONF.B.BITS = (v))
#endif
#else     //HW_OCOTP_MISC_CONF added by Pankaj
/*
 * HW_OCOTP_MISC_CONF - Value of OTP Bank5 Word5 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_misc_conf_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_MISC_CONF register
 */
#define HW_OCOTP_MISC_CONF_ADDR      (OCOTP_MISC_CONF)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_MISC_CONF           (*(volatile hw_ocotp_misc_conf_t *) HW_OCOTP_MISC_CONF_ADDR)
      #define HW_OCOTP_MISC_CONF_RD()      (HW_OCOTP_MISC_CONF.U)
      #define HW_OCOTP_MISC_CONF_WR(v)     (HW_OCOTP_MISC_CONF.U = (v))
      #define HW_OCOTP_MISC_CONF_SET(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() |  (v)))
      #define HW_OCOTP_MISC_CONF_CLR(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() & ~(v)))
      #define HW_OCOTP_MISC_CONF_TOG(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() ^  (v)))
   #else 
      #define HW_OCOTP_MISC_CONF_RD()      (_rbase->mem32_read(HW_OCOTP_MISC_CONF_ADDR))
      #define HW_OCOTP_MISC_CONF_WR(v)     (_rbase->mem32_write(HW_OCOTP_MISC_CONF_ADDR,(v)))
      #define HW_OCOTP_MISC_CONF_SET(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() |  (v)))
      #define HW_OCOTP_MISC_CONF_CLR(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() & ~(v)))
      #define HW_OCOTP_MISC_CONF_TOG(v)    (HW_OCOTP_MISC_CONF_WR(HW_OCOTP_MISC_CONF_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_MISC_CONF bitfields
 */
/* --- Register HW_OCOTP_MISC_CONF, field BITS */

#define BP_OCOTP_MISC_CONF_BITS      0
#define BM_OCOTP_MISC_CONF_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_MISC_CONF_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_MISC_CONF_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_MISC_CONF_BITS(v)   (HW_OCOTP_MISC_CONF.B.BITS = (v))
#endif

#endif

/*
 * HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_field_return_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_FIELD_RETURN register
 */
//#define HW_OCOTP_FIELD_RETURN_ADDR      (0x021bc6e0)
#define HW_OCOTP_FIELD_RETURN_ADDR      (OCOTP_FIELD_RETURN)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_FIELD_RETURN           (*(volatile hw_ocotp_field_return_t *) HW_OCOTP_FIELD_RETURN_ADDR)
      #define HW_OCOTP_FIELD_RETURN_RD()      (HW_OCOTP_FIELD_RETURN.U)
      #define HW_OCOTP_FIELD_RETURN_WR(v)     (HW_OCOTP_FIELD_RETURN.U = (v))
      #define HW_OCOTP_FIELD_RETURN_SET(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() |  (v)))
      #define HW_OCOTP_FIELD_RETURN_CLR(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() & ~(v)))
      #define HW_OCOTP_FIELD_RETURN_TOG(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() ^  (v)))
   #else 
      #define HW_OCOTP_FIELD_RETURN_RD()      (_rbase->mem32_read(HW_OCOTP_FIELD_RETURN_ADDR))
      #define HW_OCOTP_FIELD_RETURN_WR(v)     (_rbase->mem32_write(HW_OCOTP_FIELD_RETURN_ADDR,(v)))
      #define HW_OCOTP_FIELD_RETURN_SET(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() |  (v)))
      #define HW_OCOTP_FIELD_RETURN_CLR(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() & ~(v)))
      #define HW_OCOTP_FIELD_RETURN_TOG(v)    (HW_OCOTP_FIELD_RETURN_WR(HW_OCOTP_FIELD_RETURN_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_FIELD_RETURN bitfields
 */
/* --- Register HW_OCOTP_FIELD_RETURN, field BITS */

#define BP_OCOTP_FIELD_RETURN_BITS      0
#define BM_OCOTP_FIELD_RETURN_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_FIELD_RETURN_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_FIELD_RETURN_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_FIELD_RETURN_BITS(v)   (HW_OCOTP_FIELD_RETURN.B.BITS = (v))
#endif



/*
 * HW_OCOTP_SRK_REVOKE - Value of OTP Bank5 Word7 (HW Capabilities)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_srk_revoke_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_SRK_REVOKE register
 */
//#define HW_OCOTP_SRK_REVOKE_ADDR      (0x021bc6f0)
#define HW_OCOTP_SRK_REVOKE_ADDR      (OCOTP_SRK_REVOKE)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_SRK_REVOKE           (*(volatile hw_ocotp_srk_revoke_t *) HW_OCOTP_SRK_REVOKE_ADDR)
      #define HW_OCOTP_SRK_REVOKE_RD()      (HW_OCOTP_SRK_REVOKE.U)
      #define HW_OCOTP_SRK_REVOKE_WR(v)     (HW_OCOTP_SRK_REVOKE.U = (v))
      #define HW_OCOTP_SRK_REVOKE_SET(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() |  (v)))
      #define HW_OCOTP_SRK_REVOKE_CLR(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() & ~(v)))
      #define HW_OCOTP_SRK_REVOKE_TOG(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() ^  (v)))
   #else 
      #define HW_OCOTP_SRK_REVOKE_RD()      (_rbase->mem32_read(HW_OCOTP_SRK_REVOKE_ADDR))
      #define HW_OCOTP_SRK_REVOKE_WR(v)     (_rbase->mem32_write(HW_OCOTP_SRK_REVOKE_ADDR,(v)))
      #define HW_OCOTP_SRK_REVOKE_SET(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() |  (v)))
      #define HW_OCOTP_SRK_REVOKE_CLR(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() & ~(v)))
      #define HW_OCOTP_SRK_REVOKE_TOG(v)    (HW_OCOTP_SRK_REVOKE_WR(HW_OCOTP_SRK_REVOKE_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_SRK_REVOKE bitfields
 */
/* --- Register HW_OCOTP_SRK_REVOKE, field BITS */

#define BP_OCOTP_SRK_REVOKE_BITS      0
#define BM_OCOTP_SRK_REVOKE_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SRK_REVOKE_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_SRK_REVOKE_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SRK_REVOKE_BITS(v)   (HW_OCOTP_SRK_REVOKE.B.BITS = (v))
#endif


#if 0   //HDCP not there on faraday
/*
 *  multi-register-define name HW_OCOTP_HDCP_KEYn
 *              base 0x00000800
 *              count 72
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_hdcp_keyn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_HDCP_KEYn multi-register
     */
    #define HW_OCOTP_HDCP_KEYn_COUNT        72
    #define HW_OCOTP_HDCP_KEYn_ADDR(n)      (0x021bc800 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_HDCP_KEYn(n)           (*(volatile hw_ocotp_hdcp_keyn_t *) HW_OCOTP_HDCP_KEYn_ADDR(n))
    #define HW_OCOTP_HDCP_KEYn_RD(n)        (HW_OCOTP_HDCP_KEYn(n).U)
    #define HW_OCOTP_HDCP_KEYn_WR(n, v)     (HW_OCOTP_HDCP_KEYn(n).U = (v))
    #define HW_OCOTP_HDCP_KEYn_SET(n, v)    (HW_OCOTP_HDCP_KEYn_WR(n, HW_OCOTP_HDCP_KEYn_RD(n) |  (v)))
    #define HW_OCOTP_HDCP_KEYn_CLR(n, v)    (HW_OCOTP_HDCP_KEYn_WR(n, HW_OCOTP_HDCP_KEYn_RD(n) & ~(v)))
    #define HW_OCOTP_HDCP_KEYn_TOG(n, v)    (HW_OCOTP_HDCP_KEYn_WR(n, HW_OCOTP_HDCP_KEYn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_HDCP_KEYn multi-register bitfields
 */
/* --- Register HW_OCOTP_HDCP_KEYn, field BITS */

#define BP_OCOTP_HDCP_KEYn_BITS      0
#define BM_OCOTP_HDCP_KEYn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_HDCP_KEYn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_HDCP_KEYn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_HDCP_KEYn_BITS(n, v)  (HW_OCOTP_HDCP_KEYn(n).B.BITS = (v))
#endif

#else  //OCOTP_SRK_RSDV[0:4], OCOTP_TFUSE[0:1], OCOTP_PMUR, OCOTP_PMU, OCOTP_RNG, OCOTP_VTMON added by Pankaj
/*
 *  multi-register-define name OCOTP_SRK_RSDVn
 *              base 0x00000800
 *              count 5
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_srk_rsdvn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_SRK_RSDVn multi-register
     */
    #define HW_OCOTP_SRK_RSDVn_COUNT        5
    #define HW_OCOTP_SRK_RSDVn_ADDR(n)      (OCOTP_SRK_RSDV0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_SRK_RSDVn(n)           (*(volatile hw_ocotp_srk_rsdvn_t *) HW_OCOTP_SRK_RSDVn_ADDR(n))
    #define HW_OCOTP_SRK_RSDVn_RD(n)        (HW_OCOTP_SRK_RSDVn(n).U)
    #define HW_OCOTP_SRK_RSDVn_WR(n, v)     (HW_OCOTP_SRK_RSDVn(n).U = (v))
    #define HW_OCOTP_SRK_RSDVn_SET(n, v)    (HW_OCOTP_SRK_RSDVn_WR(n, HW_OCOTP_SRK_RSDVn_RD(n) |  (v)))
    #define HW_OCOTP_SRK_RSDVn_CLR(n, v)    (HW_OCOTP_SRK_RSDVn_WR(n, HW_OCOTP_SRK_RSDVn_RD(n) & ~(v)))
    #define HW_OCOTP_SRK_RSDVn_TOG(n, v)    (HW_OCOTP_SRK_RSDVn_WR(n, HW_OCOTP_SRK_RSDVn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_SRK_RSDVn multi-register bitfields
 */
/* --- Register HW_OCOTP_SRK_RSDVn, field BITS */

#define BP_OCOTP_SRK_RSDVn_BITS      0
#define BM_OCOTP_SRK_RSDVn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_SRK_RSDVn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_SRK_RSDVn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_SRK_RSDVn_BITS(n, v)  (HW_OCOTP_SRK_RSDVn(n).B.BITS = (v))
#endif



/*
 *  multi-register-define name HW_OCOTP_TFUSEn
 *              base 0x00000880
 *              count 2
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_tfusen_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_TFUSEn multi-register
     */
    #define HW_OCOTP_TFUSEn_COUNT        2
    #define HW_OCOTP_TFUSEn_ADDR(n)      (OCOTP_TFUSE0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_TFUSEn(n)           (*(volatile hw_ocotp_tfusen_t *) HW_OCOTP_TFUSEn_ADDR(n))
    #define HW_OCOTP_TFUSEn_RD(n)        (HW_OCOTP_TFUSEn(n).U)
    #define HW_OCOTP_TFUSEn_WR(n, v)     (HW_OCOTP_TFUSEn(n).U = (v))
    #define HW_OCOTP_TFUSEn_SET(n, v)    (HW_OCOTP_TFUSEn_WR(n, HW_OCOTP_TFUSEn_RD(n) |  (v)))
    #define HW_OCOTP_TFUSEn_CLR(n, v)    (HW_OCOTP_TFUSEn_WR(n, HW_OCOTP_TFUSEn_RD(n) & ~(v)))
    #define HW_OCOTP_TFUSEn_TOG(n, v)    (HW_OCOTP_TFUSEn_WR(n, HW_OCOTP_TFUSEn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_TFUSEn multi-register bitfields
 */
/* --- Register HW_OCOTP_TFUSEn, field BITS */

#define BP_OCOTP_TFUSEn_BITS      0
#define BM_OCOTP_TFUSEn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_TFUSEn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_TFUSEn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_TFUSEn_BITS(n, v)  (HW_OCOTP_TFUSEn(n).B.BITS = (v))
#endif



/*
 * HW_OCOTP_PMUR - Value of OTP Bank7 Word3 (Configuration and Manufacturing Info.)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_pmur_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_PMUR register
 */
#define HW_OCOTP_PMUR_ADDR      (OCOTP_PMUR)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_PMUR           (*(volatile hw_ocotp_pmur_t *) HW_OCOTP_PMUR_ADDR)
      #define HW_OCOTP_PMUR_RD()      (HW_OCOTP_PMUR.U)
      #define HW_OCOTP_PMUR_WR(v)     (HW_OCOTP_PMUR.U = (v))
      #define HW_OCOTP_PMUR_SET(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() |  (v)))
      #define HW_OCOTP_PMUR_CLR(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() & ~(v)))
      #define HW_OCOTP_PMUR_TOG(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() ^  (v)))
   #else 
      #define HW_OCOTP_PMUR_RD()      (_rbase->mem32_read(HW_OCOTP_PMUR_ADDR))
      #define HW_OCOTP_PMUR_WR(v)     (_rbase->mem32_write(HW_OCOTP_PMUR_ADDR,(v)))
      #define HW_OCOTP_PMUR_SET(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() |  (v)))
      #define HW_OCOTP_PMUR_CLR(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() & ~(v)))
      #define HW_OCOTP_PMUR_TOG(v)    (HW_OCOTP_PMUR_WR(HW_OCOTP_PMUR_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_PMUR bitfields
 */
/* --- Register HW_OCOTP_PMUR, field BITS */

#define BP_OCOTP_PMUR_BITS      0
#define BM_OCOTP_PMUR_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_PMUR_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_PMUR_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_PMUR_BITS(v)   (HW_OCOTP_PMUR.B.BITS = (v))
#endif



/*
 * HW_OCOTP_PMU - Value of OTP Bank7 Word4 (Configuration and Manufacturing Info.)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_pmu_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_PMU register
 */
#define HW_OCOTP_PMU_ADDR      (OCOTP_PMU)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_PMU           (*(volatile hw_ocotp_pmu_t *) HW_OCOTP_PMU_ADDR)
      #define HW_OCOTP_PMU_RD()      (HW_OCOTP_PMU.U)
      #define HW_OCOTP_PMU_WR(v)     (HW_OCOTP_PMU.U = (v))
      #define HW_OCOTP_PMU_SET(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() |  (v)))
      #define HW_OCOTP_PMU_CLR(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() & ~(v)))
      #define HW_OCOTP_PMU_TOG(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() ^  (v)))
   #else 
      #define HW_OCOTP_PMU_RD()      (_rbase->mem32_read(HW_OCOTP_PMU_ADDR))
      #define HW_OCOTP_PMU_WR(v)     (_rbase->mem32_write(HW_OCOTP_PMU_ADDR,(v)))
      #define HW_OCOTP_PMU_SET(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() |  (v)))
      #define HW_OCOTP_PMU_CLR(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() & ~(v)))
      #define HW_OCOTP_PMU_TOG(v)    (HW_OCOTP_PMU_WR(HW_OCOTP_PMU_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_PMU bitfields
 */
/* --- Register HW_OCOTP_PMU, field BITS */

#define BP_OCOTP_PMU_BITS      0
#define BM_OCOTP_PMU_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_PMU_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_PMU_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_PMU_BITS(v)   (HW_OCOTP_PMU.B.BITS = (v))
#endif



/*
 * HW_OCOTP_RNG - Value of OTP Bank7 Word5 (Configuration and Manufacturing Info.)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_rng_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_RNG register
 */
#define HW_OCOTP_RNG_ADDR      (OCOTP_RNG)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_RNG           (*(volatile hw_ocotp_rng_t *) HW_OCOTP_RNG_ADDR)
      #define HW_OCOTP_RNG_RD()      (HW_OCOTP_RNG.U)
      #define HW_OCOTP_RNG_WR(v)     (HW_OCOTP_RNG.U = (v))
      #define HW_OCOTP_RNG_SET(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() |  (v)))
      #define HW_OCOTP_RNG_CLR(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() & ~(v)))
      #define HW_OCOTP_RNG_TOG(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() ^  (v)))
   #else 
      #define HW_OCOTP_RNG_RD()      (_rbase->mem32_read(HW_OCOTP_RNG_ADDR))
      #define HW_OCOTP_RNG_WR(v)     (_rbase->mem32_write(HW_OCOTP_RNG_ADDR,(v)))
      #define HW_OCOTP_RNG_SET(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() |  (v)))
      #define HW_OCOTP_RNG_CLR(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() & ~(v)))
      #define HW_OCOTP_RNG_TOG(v)    (HW_OCOTP_RNG_WR(HW_OCOTP_RNG_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_RNG bitfields
 */
/* --- Register HW_OCOTP_RNG, field BITS */

#define BP_OCOTP_RNG_BITS      0
#define BM_OCOTP_RNG_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_RNG_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_RNG_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_RNG_BITS(v)   (HW_OCOTP_RNG.B.BITS = (v))
#endif



/*
 * HW_OCOTP_VTMON - Value of OTP Bank7 Word7 (Configuration and Manufacturing Info.)
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_vtmon_t;
#endif

/*
 * constants & macros for entire HW_OCOTP_VTMON register
 */
#define HW_OCOTP_VTMON_ADDR      (OCOTP_VTMON)

#ifndef __LANGUAGE_ASM__
   #ifndef ROCOO_TEST
      #define HW_OCOTP_VTMON           (*(volatile hw_ocotp_vtmon_t *) HW_OCOTP_VTMON_ADDR)
      #define HW_OCOTP_VTMON_RD()      (HW_OCOTP_VTMON.U)
      #define HW_OCOTP_VTMON_WR(v)     (HW_OCOTP_VTMON.U = (v))
      #define HW_OCOTP_VTMON_SET(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() |  (v)))
      #define HW_OCOTP_VTMON_CLR(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() & ~(v)))
      #define HW_OCOTP_VTMON_TOG(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() ^  (v)))
   #else 
      #define HW_OCOTP_VTMON_RD()      (_rbase->mem32_read(HW_OCOTP_VTMON_ADDR))
      #define HW_OCOTP_VTMON_WR(v)     (_rbase->mem32_write(HW_OCOTP_VTMON_ADDR,(v)))
      #define HW_OCOTP_VTMON_SET(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() |  (v)))
      #define HW_OCOTP_VTMON_CLR(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() & ~(v)))
      #define HW_OCOTP_VTMON_TOG(v)    (HW_OCOTP_VTMON_WR(HW_OCOTP_VTMON_RD() ^  (v)))
   #endif 
#endif


/*
 * constants & macros for individual HW_OCOTP_VTMON bitfields
 */
/* --- Register HW_OCOTP_VTMON, field BITS */

#define BP_OCOTP_VTMON_BITS      0
#define BM_OCOTP_VTMON_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_VTMON_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_VTMON_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_VTMON_BITS(v)   (HW_OCOTP_VTMON.B.BITS = (v))
#endif

#endif  //OCOTP_SRK_RSDV[0:4], OCOTP_TFUSE[0:1], OCOTP_PMUR, OCOTP_PMU, OCOTP_RNG, OCOTP_VTMON added by Pankaj



/*
 *  multi-register-define name HW_OCOTP_CRCn
 *              base 0x00000900
 *              count 8
 *              offset 0x10
 */
#ifndef __LANGUAGE_ASM__
typedef union
{
    reg32_t  U;
    struct
    {
        unsigned BITS  : 32;
    } B;
} hw_ocotp_crcn_t;
#endif

    /*
     * constants & macros for entire HW_OCOTP_CRCn multi-register
     */
    #define HW_OCOTP_CRCn_COUNT        8
    //#define HW_OCOTP_CRCn_ADDR(n)      (0x021bcd00 + ((n) * 0x10))
    #define HW_OCOTP_CRCn_ADDR(n)      (OCOTP_CRC0 + ((n) * 0x10))

    #ifndef __LANGUAGE_ASM__
    #define HW_OCOTP_CRCn(n)           (*(volatile hw_ocotp_crcn_t *) HW_OCOTP_CRCn_ADDR(n))
    #define HW_OCOTP_CRCn_RD(n)        (HW_OCOTP_CRCn(n).U)
    #define HW_OCOTP_CRCn_WR(n, v)     (HW_OCOTP_CRCn(n).U = (v))
    #define HW_OCOTP_CRCn_SET(n, v)    (HW_OCOTP_CRCn_WR(n, HW_OCOTP_CRCn_RD(n) |  (v)))
    #define HW_OCOTP_CRCn_CLR(n, v)    (HW_OCOTP_CRCn_WR(n, HW_OCOTP_CRCn_RD(n) & ~(v)))
    #define HW_OCOTP_CRCn_TOG(n, v)    (HW_OCOTP_CRCn_WR(n, HW_OCOTP_CRCn_RD(n) ^  (v)))
    #endif


/*
 * constants & macros for individual HW_OCOTP_CRCn multi-register bitfields
 */
/* --- Register HW_OCOTP_CRCn, field BITS */

#define BP_OCOTP_CRCn_BITS      0
#define BM_OCOTP_CRCn_BITS      0xFFFFFFFF

#ifndef __LANGUAGE_ASM__
#define BF_OCOTP_CRCn_BITS(v)   ((reg32_t) v)
#else
#define BF_OCOTP_CRCn_BITS(v)   (v)
#endif
#ifndef __LANGUAGE_ASM__
#define BW_OCOTP_CRCn_BITS(n, v)  (HW_OCOTP_CRCn(n).B.BITS = (v))
#endif


#endif /* _OCOTP_H */

////////////////////////////////////////////////////////////////////////////////
